How can there be pshufb patents other than Intel's 2003 patent?

[#1]

Intel's 2003 patent: Method and apparatus for parallel table lookup using SIMD instructions

https://patents.google.com/patent/US20040054879A1/en

In July 2006, Intel noted that PSHUFB was available on the Core 2 Duo CPUs, such as the X6800, to some companies and universities working with error correction code. I recall some published programs that were using it later on that year (around September 2006). However I've seen one or more later patents (2010 or later) that include using PSHUFB for parallel table lookup, which doesn't make sense.

[#2]

Hello @samlex, 

Thanks for joining our community. 

I do not know exactly how this fits Cloudera scope, but very interesting question. 

Reading some other information and searching for that, I found other patents that do have PSHUFB used. 
For example: 
https://patents.google.com/patent/US11848686B2/en 
https://patents.google.com/patent/US11362678B2/en 

Can you tells us more how this relates to Cloudera? Maybe we can get some specific help on that field if this applies. 

[#3]

"how this relates to Cloudera?": there was some lawsuit regarding usage of the code in Intel's ISA-L repository, but I don't know if the patents you mentioned were involved. Intel faced a similar lawsuit, but that was dismissed in 2022 due to an NDA.  I don't know if the Intel lawsuit had any effect on the Cloudera lawsuit.

As for PSHUFB patents, most of them are a series of patents filed by William W. Macy, Jr. and others at Intel:

https://patents.justia.com/inventor/william-w-macy-jr?page=3

Several of those patents were filed in 2003, but granted in 2010, and 2010 was the first year that Intel included PSHUFB in a processor. Did those patents require an actual hardware implementation before they could be granted?

Looking at the patents you linked to, aren't some of those claims essentially duplicates of Intel's patent claims?

The point of Intel's ISA-L (Intelligent Storage Acceleration) is to take advantage of instructions that that speed up stuff like CRC (X86 - pclmulqdq) or erasure or error correcting code (X86 - pshufb, vgf2p8affineqb, ...). The most recent activity has been for RISC-V. I worked with LTO tape drives that implemented hardware error correction code on a matrix with a lot of parallel operations, while software was used during development. Some of the software and hardware developers in the tape drive community were doing this stuff back in the mid 1980's.